A through-silicon via (TSV) is a vertical electrical connection that passes through a silicon (Si) substrate (e.g., silicon wafer/die) from an upper surface thereof to an opposing lower surface thereof. Typically, a TSV is formed by first etching the Si substrate to define a through-hole passing from the upper surface to the opposing lower surface. Then, a layer of dielectric material, such as silicon dioxide (SiO2), is deposited along the interior sidewall surface(s) of the through-hole in the substrate. Finally, an electrically conductive material, such as copper (Cu), is deposited in the remainder of the through-hole to provide an electrical connection between the upper and lower surfaces of the substrate. TSVs may be used to interconnect multiple active circuit layers (e.g., stacked chips) in a single chip or multiple dies, thereby forming a three-dimensional integrated circuit (3D IC) or other three-dimensional package.
These and other features of the present embodiments will be understood better by reading the following detailed description, taken together with the figures herein described. In the drawings, each identical or nearly identical component that is illustrated in various figures may be represented by a like numeral. For purposes of clarity, not every component may be labeled in every drawing. Furthermore, as will be appreciated, the figures are not necessarily drawn to scale or intended to limit the described embodiments to the specific configurations shown. For instance, while some figures generally indicate straight lines, right angles, and smooth surfaces, an actual implementation of the disclosed techniques may have less than perfect straight lines, right angles, etc., and some features may have surface topology or otherwise be non-smooth, given real world limitations of fabrication processes. In short, the figures are provided merely to show example structures.